VLSI & Embedded Systems (VES) Lab

Location : Main Block
Room No :  MB-015
Area    : 72 m2

This Lab is meant for PG Students for conducting experiments in the field of VLSI & Embedded Systems. The lab is equipped with FPGA boards like Spartan Starter Kits, 40 desktop computers, 32 channel logic analyser, PIC Microcontroller Development Board, ARM Development Boards, AVR Atmega Boards, PCB prototyping system etc.

The software installed in this lab are, Design Software, Xilinx ISE, ASIC flow, Cadence, Orcad, T-CAD etc.

Computer Systems
PCB Prototype Machine
Logic State Analyser
Function Generator
1. Combinational Circuits

(a) Multiplexer 4X1 using (i) when else statement (ii) with select statement (iii) case statement (d) If else statement
(b) Binary to Gray converter and Gray to binary converter using mode control
(c) Full adder and Full subtractor using mode control

2. Sequential Circuits

(a) Asynchronous and synchronous D type and JK type flip flops
(b) 4 bit loadable up/down counter
(c) 4 bit shift register with left, right shift controls and load option.

3. Structural Design

(a) 4 bit adder using component instantiation
(b) 4 bit Barrel shift register using component instantiation

4. Design using Packages, functions and Procedures

(a) Design a ALU using Procedure statement
(b) Design a 8kX8 RAM using package. Necessary functions, components can be stored in the user library

5. Design using Test Benches

(a) Design a test bench for testing a AND-OR (Y=ab+cd) logic.
(b) Design a test bench for testing a chocolate vending machine which accepts Rs. 5 and Rs. 10 coins and dispenses a chocolate for every Rs. 15. If the customer inserts a total of Rs. 20, it will wait for another Rs. 10 for dispensing another chocolate, without returning the balance.

6. Finite State Machine Design

(a) Design a 8 bit serial adder with accumulator having start, load, shift controls. Use Moore Type machine for implementing both control FSM and serial adder FSM.
(b) Design a 4 bit multiplier with start, load, shift, add controls using Mealy machine


Prof. U. Sajesh Kumar

Technical Staff

Samresh M. K.
Prakashan Panayan